In this post we will explain shortly how to implement a simple Vga Driver to be used in fpga projects that require image display. We used this code for the Space Invaders Project and we decided to modify it a bit in order to function as an independent module.
The code for this project is available here.
Each line of the video begins with an active video region, in which RGB values are output for each pixel in the line. Then a blanking region follows in which a horizontal sync pulse is transmitted in the middle of the blanking interval. The interval before the sync pulse is known as front porch and after the sync pulse back porch.
For our project we had a resolution of 640×480@60Hz, so we created a 50 MHz clock, from the 100 MHz clock input of the Zedboard and the horizontal and the vertical count have a total value of 800 and 524 respectively. Based on these numbers we calculate the exact time that the hsync and vsync are set active high (both signals on this resolution must be active high) and we connect them to the FPGA pins.