LCD Driver for Sparta-3e FPGA


The Verilog code for this project is available here.


The purpose of this project is the implementation of a LCD driver for the Spartan-3e FPGA. The implementation is not specific for this FPGA only but it can be used in any LCD using the SITRONIX ST7066U controller. The output message in the LCD for testing is: ABCDEDFGHIJKLMNOP in the upper row and for the lower row: abcdefghijklmno and the blinking cursor at the end of the line with a refresh rate of 1 sec. The message is stored in a BRAM of the Spartan-3e.


Before we attempt to print any message in the LCD, we have to initiate it through its controller. This is a standard procedure that includes certain steps which will be explained later. So, for the implementation of the driver he had to design two FSMs, one of which is responsible for the initiation of the LCD, while the second one is used for the printing of the message. In the beginning the first FSM starts and according the initiation protocol sends the commands to the controller respecting the appropriate timings. After that the first FSMs uses the second one to print the message to the LCD. Finally the first FSM enters an state in which its only goal is to command the second FSM to keep its work. If we press the reset button, the processes start over again.

Part 1: Design of the first FSM

Function: We used a counter that increments in every clock cycle, a variable named bell counter which is set in each state to the amount of time needed to move from this state to the next one, and one variable “bell” which is high only when the counter reaches the value of the bell counter. This variable “bell” is actually the control signal of the multiplexor that chooses the state.

Implentation: This FSM is implemented using a counter according to the timings of the manual, enters a specific states and performs the initialization steps.

Here are the states, their descriptions and the condition in order to change to the next state.


Part 2: Design of the second FSM.

The function and the implementation of this FSM is very similar to the first one.

Here are the states, their descriptions and the condition in order to change to the next state.


Final Step on the FPGA video.


For any questions leave a comment !!